Fault tolerant systems must provide a specified level of service after a fault has occurred. High criticality systems require that faults be tolerated that have a probability of occurrence between 10−9 to 10−6 for a one hour exposure. Typically the desired level of fault tolerances must be proven to be met by a combination of analysis and testing. The ability to detect and mitigate a fault is called coverage. The overall system failure probability includes the combination of component fault probability and coverage percentage. For electronic components (typically integrated circuits) used in the environment where highly dependable electronic systems are acquired, one assumes a component failure probability of 10−6 for a one hour exposure. Moreover, with multiple components in a system, one can assume an overall failure rate in the range of 10−4 to 10−5 for a one hour exposure.
Byzantine faults comprise a class of faults that are particularly difficult cover. A Byzantine fault is a fault that presents different outputs to multiple observers. For example, in a logic circuit having an input and multiple redundant outputs, if different observers of the outputs observe different outputs in response to an input, a Byzantine fault is present. Even if the logic circuit has only a single output with multiple observers, each observer can view the output signal differently due to the behavior of a Byzantine fault. Byzantine faults occur in two dimensions, amplitude and time. Regarding amplitude, a Byzantine fault can cause signals traveling through elements in the logic circuit to not be clearly defined as a “logic 1” or a “logic 0.” These signals fall somewhere in between the signal level defined as logic 1 and logic 0. These so called “½ logic signals” or “indeterminate logic signals” can be interpreted by different elements in the logic circuits as either a logic 1 or a logic 0. However, not every element in the logic circuit will make the same determination. This is due to manufacturing variances in the logic devices or to such environmental factors as voltage variances and temperature variances. In the time dimension, Byzantine faults can occur in the micro and macro scale. In the micro scale, the faults occur at the bit level wherein the bits are formed too narrow or too wide. At the macro scale, Byzantine faults typically occur due to missing communication signal deadlines. Moreover, Byzantine faults occur more often in the time domain than in the amplitude domain.
For highly critical applications that require system failure probabilities in the neighborhood of 10−9 for a one hour exposure, methods have to be developed to handle the ½ logic signals. One method of dealing with Byzantine faults is with a filtering device that reshapes ½ logic signals to valid logic signals before the logic signal is observed by the observers. Once the Byzantine faults have been dealt within a filter circuit design, proof of the design's fault coverage is required. Commonly assigned patent application Ser. No. 10/993,398, filed on Nov. 19, 2004 provided a method to prove a design's fault coverage. Reducing the voltage range that needs to be tested would improve the efficiency in providing design fault coverage.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon observing and understanding the present specification, there is a need in the art for a method of improving the efficiency of proving a design's fault coverage.